Bus Timing - Hitachi SH7750 series Hardware Manual

Superh risc engine
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23.3.3

Bus Timing

Table 23.16 Bus Timing
(V
= 3.0 to 3.6 V, V
DDQ
Item
Symbol
Address delay time
t
%6 delay time
t
&6 delay time
t
5: delay time
t
5' delay time
t
Read data setup
t
time
Read data hold
t
time
:( delay time
t
(falling edge)
:( delay time
t
Write data delay
t
time
5'< setup time
t
5'< hold time
t
5$6 delay time
t
&$6 delay time 1
t
&$6 delay time 2
t
CKE delay time
t
DQM delay time
t
)5$0( delay time
t
,2,649 setup time
t
,2,649 hold time
t
,&,2:5 delay time
t
(falling edge)
= typ. 1.8 V, T
DD
HD6417750
VF128
1
64 MHz*
Min
Max
10
AD
10
BSD
10
CSD
10
RWD
10
RSD
3.5
RDS
1.5
RDH
10
WEDF
10
WED1
10
WDD
3.5
RDYS
1.5
RDYH
10
RASD
10
CASD1
10
CASD2
10
CKED
10
DQMD
10
FMD
3.5
IO16S
1.5
IO16H
10
ICWSDF
= –20 to +75°C, C
a
L
HD6417750
HD6417750
HD6417750
HD6417750
SVF133
SF167
2
67 MHz*
83 MHz*
Min
Max
Min
10
10
10
10
10
3.5
3.5
1.5
1.5
10
10
10
3.5
3.5
1.5
1.5
10
10
10
10
10
10
3.5
3.5
1.5
1.5
10
= 30 pF, PLL2 on)
F167
HD6417750
F167I
BP200M
HD6417750
SBP200
3
100 MHz*
Max
Min
Max
8
6
8
6
8
6
8
6
8
6
3
1.5
8
6
8
6
8
6
3
1.5
8
6
8
6
8
6
8
6
8
6
8
6
3
1.5
8
6
Rev. 4.0, 04/00, page 757 of 850
4
Unit
Notes
ns
ns
ns
ns
ns
ns
ns
ns
Relative
to CKIO
falling
edge
ns
ns
ns
ns
ns
ns
DRAM
ns
SDRAM
ns
SDRAM
ns
SDRAM
ns
MPX
ns
ns
PCMCIA
ns
PCMCIA

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