Hitachi SH7750 series Hardware Manual page 609

Superh risc engine
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Initialization
Clear TE and RE bits
in SCSCR2 to 0
Set TFRST and RFRST bits
in SCFCR2 to 1
Set CKE1 bit in SCSCR2
(leaving TE and RE bits
cleared to 0)
Set data transfer format
in SCSMR2
Set value in SCBRR2
1-bit interval elapsed?
Set RTRG1–0, TTRG1–0,
and MCE bits in SCFCR2
Clear TFRST and RFRST bits to 0
Set TE and RE bits
in SCSCR2 to 1,
and set RIE, TIE, and REIE bits
Rev. 4.0, 04/00, page 598 of 850
Wait
No
Yes
End
Figure 16.7 Sample SCIF Initialization Flowchart
1. Set the clock selection in SCSCR2.
Be sure to clear bits RIE and TIE,
and bits TE and RE, to 0.
2. Set the data transfer format in
SCSMR2.
3. Write a value corresponding to the
bit rate into SCBRR2. (Not
necessary if an external clock is
used.)
4. Wait at least one bit interval, then
set the TE bit or RE bit in SCSCR2
to 1. Also set the RIE, REIE, and
TIE bits.
Setting the TE and RE bits enables
the TxD2 and RxD2 pins to be
used. When transmitting, the SCIF
will go to the mark state; when
receiving, it will go to the idle state,
waiting for a start bit.

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