Hitachi SH7750 series Hardware Manual page 558

Start
1
bit
Serial
0 D0 D1
data
TDRE
TEND
Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data,
Multiprocessor Serial Data Reception: Figure 15.15 shows a sample flowchart for
multiprocessor serial reception.
Use the following procedure for multiprocessor serial data reception after enabling the SCI for
reception.
Multi-
Data Stop
proces-
sor bit bit
D7 1 1
One frame
MPBT bit cleared to 0, data
written to SCTDR1, and
TDRE flag cleared to 0 by
TEI interrupt handler
Multiprocessor Bit, One Stop Bit)
Multi-
Start Data
proces-
bit sor bit
0 D0 D1 D7 0
Data written to SCTDR1
and TDRE flag cleared
to 0 by TXI interrupt
handler
Stop Start Data
bit bit
1 0 D0 D1 D7
TXI interrupt
request
Rev. 4.0, 04/00, page 547 of 850
Multi-
Stop
proces-
1
sor bit bit
Idle state
0
(mark state)
TEI interrupt
request