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Section 15 Serial Communication Interface (SCI)
15.1
Overview
The SH7750 is equipped with a single-channel serial communication interface (SCI) and a single-
channel serial communication interface with built-in FIFO registers (SCI with FIFO: SCIF).
The SCI can handle both asynchronous and synchronous serial communication. A function is also
provided for serial communication between processors (multiprocessor communication function).
The SCI supports a smart card interface conforming to ISO/IEC 7816-3 (Identification Card) as a
serial communication interface function for IC card interface use. For details, see section 17,
Smart Card Interface.
The SCIF is a dedicated asynchronous communication serial interface with built-in 16-stage FIFO
registers for both transmission and reception. For details, see section 16, Serial Communication
Interface with FIFO.
15.1.1
Features
SCI features are listed below.
• Choice of synchronous or asynchronous serial communication mode
Asynchronous mode
Serial data communication is executed using an asynchronous system in which
synchronization is achieved character by character. Serial data communication can be
carried out with standard asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface
Adapter (ACIA). A multiprocessor communication function is also provided that enables
serial data communication with a number of processors.
There is a choice of 12 serial data transfer formats.
Data length:
Stop bit length:
Parity:
Multiprocessor bit:
Receive error detection: Parity, overrun, and framing errors
Break detection:
7 or 8 bits
1 or 2 bits
Even/odd/none
1 or 0
A break can be detected by reading the RxD pin level directly
from the serial port register (SCSPTR1) when a framing error
occurs.
Rev. 4.0, 04/00, page 503 of 850
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