Hitachi SH7750 series Hardware Manual page 289

Bits 7 to 5—Area 6 Burst Enable (A6BST2–A6BST0): These bits specify whether burst ROM
interface is used in area 6. When burst ROM interface is used, they also specify the number of
accesses in a burst. If area 6 is an MPX interface area, these bits are ignored.
Bit 7: A6BST2 Bit 6: A6BST1
0 0
1
1 0
1
Note: Clear to 0 when PCMCIA interface is set.
Rev. 4.0, 04/00, page 278 of 850
Bit 5: A6BST0 Description
0 Area 6 is accessed as SRAM interface
1 Area 6 is accessed as burst ROM
interface (4 consecutive accesses)
Can be used with 8-, 16-, or 32--bit bus
width
0 Area 6 is accessed as burst ROM
interface (8 consecutive accesses)
Can be used with 8-, 16-, or 32-bit bus
width
1 Area 6 is accessed as burst ROM
interface (16 consecutive accesses)
Can only be used with 8- or 16-bit bus
width. Do not specify for 32-bit bus width
0 Area 6 is accessed as burst ROM
interface (32 consecutive accesses)
Can only be used with 8-bit bus width
1 Reserved
0 Reserved
1 Reserved
(Initial value)