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As the CPU in the SH7750 Series is connected to cache memory by a dedicated internal bus,
reading from cache memory can still be carried out when the bus is being used by another bus
master inside or outside the SH7750 Series. When writing from the CPU, an external write cycle
is generated when write-through has been set for the cache in the SH7750 Series, or when an
access is made to a cache-off area. There is consequently a delay until the bus is returned.
When the SH7750 Series wants to take back the bus in response to an internal memory refresh
request, it negates %$&.. On receiving the %$&. negation, the device that asserted the external
bus release request negates %5(4 to release the bus. The bus is thereby returned to the SH7750
Series, which then carries out the necessary processing.
Rev. 4.0, 04/00, page 413 of 850
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