Hitachi SH7750 series Hardware Manual page 272

Table 13.1 BSC Pins (cont)
Name
Data enable 1
Data enable 2
Data enable 3
Data enable 4
Data enable 5
Signals I/O
:(4/&$64/
O
DQM1
:(5/&$65/
O
DQM2/,&,25'
:(6/&$66/
O
DQM3/,&,2:5
:(7/&$67/
O
DQM4
:(8/&$68/
O
DQM5
Description
When setting synchronous DRAM interface:
selection signal for D15–D8
When setting DRAM interface: &$6 signal for
D15–D8
When setting PCMCIA interface: write strobe signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D15–D8
When setting synchronous DRAM interface:
selection signal for D23–D16
When setting DRAM interface: &$6 signal for
D23–D16
When setting PCMCIA interface: ,&,25' signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D23–D16
When setting synchronous DRAM interface:
selection signal for D31–D24
When setting DRAM interface: &$6 signal for
D31–D24
When setting PCMCIA interface: ,&,2:5 signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D31–D24
When setting synchronous DRAM interface:
selection signal for D39–D32
When setting DRAM interface: &$6 signal for
D39–D32
When setting MPX interface: high-level output
In other cases: write strobe signal for D39–D32
When setting synchronous DRAM interface:
selection signal for D47–D40
When setting DRAM interface: &$6 signal for
D47–D40
When setting MPX interface: high-level output
In other cases: write strobe signal for D47–D40
Rev. 4.0, 04/00, page 261 of 850