Hitachi SH7750 series Hardware Manual page 779

CKIO
BANK
Precharge-sel
Addr
RD/
DQMn
D63–D0
(read)
D63–D0
(write)
CKE
DACKn
(SA: IO ← memory)
Figure 23.27 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst
Tc1 Tc2 Tc3
t
AD
Row
H/L
c0
t
CSD
t
RWD
t
RASD
t t
CASD2 CASD2
t
DQMD
t
WDD
t
DACD
(CAS Latency = 3)
Td3
Tc4/Td1 Td2
t
DQMD
t t
RDS RDH
d0 d1
t t
BSD BSD
t
DACD
Rev. 4.0, 04/00, page 771 of 850
Td4
t
AD
t
CSD
t
RWD
t
RASD
d2 d3
t
WDD
t
DACD