Hitachi SH7750 series Hardware Manual page 791

CKIO
A25–A0
RD/
D63–D0
(read)
D63–D0
(write)
DACKn
(SA: IO ← memory)
Figure 23.38 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)
T1r Tr2 Tc1
t t
AD AD
Row
t
CSD
t
RWD
t t
RASD RASD
t t
CASD1 CASD1
t
WDD
t
BSD
t
t
DACD
DACD
Tce Tpc
Tc2
t
AD
column
t
CSD
t
RASD
t
CASD1
t t
RDS RDH
t
BSD
Rev. 4.0, 04/00, page 783 of 850
t
RWD