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addresses in the same bank, the PRE command cannot be issued until the last-but-one data latch
cycle. If a read access is followed by a write access, it may be possible to issue a PRE or ACT
command, depending on the bank and row address, but since the write data is output at the same
time as the WRIT command, the PRE, ACTV, and WRIT commands are issued in such a way that
one or two empty cycles occur automatically on the data bus. Similarly, with a read access
following a write access, or a write access following a write access, the PRE, ACTV, READ, or
WRIT command is issued during the data write cycle for the preceding access; however, in the
case of different row addresses in the same bank, a PRE command cannot be issued, and so in this
case the PRE command is issued following the number of Trwl cycles specified by the TRWL bits
in MCR, after the end of the last data write cycle.
Figure 13.36 shows a burst read cycle for a different bank and row address following a preceding
burst read cycle.
Pipelined access is enabled only for consecutive access to area 3, and will be discontinued in the
event of an access to another area. Pipelined access is also discontinued in the event of a refresh
cycle, or bus release due to bus arbitration. The cases in which pipelined access is available are
shown in table 13.16. In this table, "DMAC dual" indicates transfer in DMAC dual address mode,
and "DMAC single", transfer in DMAC single address mode.
Table 13.16 Cycles in Which Pipelined Access Can Be Used
Preceding Access
CPU
Read
Write
DMAC dual
Read
Write
DMAC single
Read
Write
O: Pipelined access possible
X: Pipelined access not possible
Rev. 4.0, 04/00, page 366 of 850
CPU
Read
Write
X
X
X
X
X
X
O
O
O
O
O
O
Following Access
DMAC Dual
Read
Write
O
X
O
X
X
X
O
X
X
X
O
X
DMAC Single
Read
Write
O
O
O
O
X
X
O
O
O
O
O
O
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