Hitachi SH7750 series Hardware Manual page 387

T1 Tw Tw TB2 TB1 Tw TB2 TB1 Tw TB2 TB1 Tw T2
CKIO
A25–A5
A4–A0
RD/
D63–D0
(read)
DACKn
(SA: IO ← memory)
Note: For a write cycle, a basic bus cycle (write cycle) is performed.
Figure 13.42 Burst ROM Wait Access Timing
Rev. 4.0, 04/00, page 376 of 850