Hitachi SH7750 series Hardware Manual page 785

Figure 23.33 Synchronous DRAM Bus Cycle: Synchronous DRAM Precharge Command
Tpr
CKIO
t
AD
BANK Row
Precharge-sel
H/L
Addr
t
CSD
t
RWD
RD/
t
RASD
t
CASD2
t
DQMD
DQMn
t
WDD
D63–D0
(write)
CKE
t
DACD
DACKn
(TPC = 1)
Tpc
t
AD
t
CSD
t
RWD
t
RASD
t
CASD2
t
DQMD
t
WDD
t
BSD
t
DACD
Rev. 4.0, 04/00, page 777 of 850