External Memory Space - Hitachi SH7750 series Hardware Manual

H'0000 0000
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
P0, P1, P3, U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or
not the cache is used is determined by the cache control register (CCR). When the cache is used,
with the exception of the P1 area, switching between the copy-back method and the write-through
method for write accesses is specified by the CCR.WT bit. For the P1 area, switching is specified
by the CCR.CB bit. Zeroizing the upper 3 bits of an address in these areas gives the corresponding
external memory space address. However, since area 7 in the external memory space is a reserved
area, a reserved area also appears in these areas.
P2 Area: The P2 area cannot be accessed using the cache. In the P2 area, zeroizing the upper 3
bits of an address gives the corresponding external memory space address. However, since area 7
in the external memory space is a reserved area, a reserved area also appears in this area.
P4 Area: The P4 area is mapped onto SH7750 Series on-chip I/O channels. This area cannot be
accessed using the cache. The P4 area is shown in detail in figure 3.4.
P0 area
Cacheable
P1 area
Cacheable
P2 area
Non-cacheable
P3 area
Cacheable
P4 area
Non-cacheable
Privileged mode
Figure 3.3 Physical Memory Space (MMUCR.AT = 0)
External
memory space
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
Store queue area
H'0000 0000
U0 area
Cacheable
H'8000 0000
Address error
H'E000 0000
H'E400 0000
Address error
H'FFFF FFFF
User mode
Rev. 4.0, 04/00, page 33 of 850