Hitachi SH7750 series Hardware Manual page 523

Superh risc engine
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Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt
(TXI) request generation when serial transmit data is transferred from SCTDR1 to SCTSR1 and
the TDRE flag in SCSSR1 is set to 1.
Bit 7: TIE
0
1
Note: * TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it to 0,
or by clearing the TIE bit to 0.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI)
request and receive-error interrupt (ERI) request generation when serial receive data is transferred
from SCRSR1 to SCRDR1 and the RDRF flag in SCSSR1 is set to 1.
Bit 6: RIE
0
1
Note: * RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF flag, or the
FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5: TE
0
1
Notes: 1. The TDRE flag in SCSSR1 is fixed at 1.
2. In this state, serial transmission is started when transmit data is written to SCTDR1 and
the TDRE flag in SCSSR1 is cleared to 0.
SCSMR1 setting must be performed to decide the transmit format before setting the TE
bit to 1.
Rev. 4.0, 04/00, page 512 of 850
Description
Transmit-data-empty interrupt (TXI) request disabled*
Transmit-data-empty interrupt (TXI) request enabled
Description
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI)
request disabled*
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI)
request enabled
Description
Transmission disabled*
Transmission enabled*
1
2
(Initial value)
(Initial value)
(Initial value)

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