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VA is
VA is
in P4 area
in P2 area
On-chip I/O access
No
Data TLB miss
exception
PR?
00 or
01
W
R/W?
Data TLB protection
violation exception
Cache access
in copy-back mode
Figure 3.10 Flowchart of Memory Access Using UTLB
Data access to virtual address (VA)
VA is
in P1 area
0
CCR.OCE?
1
0
CCR.CB?
1
VPNs match
and V = 1
Yes
0 (User)
11
10
W
R/W?
R
R
Initial page write
exception
and CCR.OCE = 1
0
Cache access
in write-through mode
No
MMUCR.AT = 1
CCR.WT?
0
SH = 0
No
and (MMUCR.SV = 0 or
SR.MD = 0)
VPNs match
No
and ASIDs match and
V = 1
Only one
entry matches
SR.MD?
1 (Privileged)
Memory access
01 or 11
W
R/W?
R
1
D?
0
C = 1
No
Yes
WT?
1
Rev. 4.0, 04/00, page 43 of 850
VA is in P0, U0,
or P3 area
Yes
Yes
Yes
No
Yes
Data TLB multiple
hit exception
00 or 10
W
R/W?
R
Data TLB protection
violation exception
Memory access
(Non-cacheable)
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