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memory in the write cycle. Figure 14.8 shows the timing for this operation. The DACK output
timing is the same as that of &6Q in a read or write cycle specified by the CHCRn.AM bit.
DMAC
BSC
Taking the SAR value as the address, data is read from the transfer source module
and stored temporarily in the data buffer in the bus state controller (BSC).
DMAC
BSC
Taking the DAR value as the address, the data stored in the BSC's data buffer is
written to the transfer destination module.
Rev. 4.0, 04/00, page 450 of 850
SAR
DAR
Data buffer
1st bus cycle
SAR
DAR
Data buffer
2nd bus cycle
Figure 14.7 Operation in Dual Address Mode
Memory
Transfer source
module
Transfer destination
module
Memory
Transfer source
module
Transfer destination
module
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