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Bits 31 to 0—Break Data B31 to B0 (BDB31–BDB0): These bits hold the data (bits 31–0) to be
used in the channel B break conditions.
20.2.10 Break Data Mask Register B (BDMRB)
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Note: *: Undefined
Break data mask register B (BDMRB) is a 32-bit readable/writable register that specifies which
bits of the break data set in BDRB are to be masked. BDMRB is not initialized by a power-on
reset or manual reset.
Rev. 4.0, 04/00, page 686 of 850
31
30
BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24
*
*
R/W
R/W
23
22
BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16
*
*
R/W
R/W
15
14
BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8
*
*
R/W
R/W
7
6
BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0
*
*
R/W
R/W
29
28
*
*
R/W
R/W
21
20
*
*
R/W
R/W
13
12
*
*
R/W
R/W
5
4
*
*
R/W
R/W
27
26
*
*
R/W
R/W
19
18
*
*
R/W
R/W
11
10
*
*
R/W
R/W
3
2
*
*
R/W
R/W
25
24
*
*
R/W
R/W
17
16
*
*
R/W
R/W
9
8
*
*
R/W
R/W
1
0
*
*
R/W
R/W
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