Hitachi SH7750 series Hardware Manual page 498

CLK
DBREQ
BAVL
TR
A25–A0
D63–D0
RAS, CAS,
WE
Figure 14.34 Read from Synchronous DRAM Precharge Bank
CLK
DBREQ
BAVL
TR
A25–A0
D63–D0
RAS, CAS,
WE
Figure 14.35 Read from Synchronous DRAM Non-Precharge Bank (Row Miss)
RA CA
BA RD
Transfer requests can be accepted
RA
BA
PCH
D0 D1 D2 D3
CA
D0 D1
RD
Rev. 4.0, 04/00, page 487 of 850
D2 D3