Hitachi SH7750 series Hardware Manual page 771

CKIO
A25–A5
A4–A0
RD/
D31–D0
(read)
DACKn
(SA: IO ← memory)
DACKn
(DA)
Note: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
T1 TB2 TB1
t
AD
t
CSD
t
RWD
t
RSD
t
RSD
t
RDS
t t
BSD BSD
t t
DACD DACD
t
DACD
Figure 23.19 Burst ROM Bus Cycle (No Wait)
TB2 TB1 TB2
t
AD
t
RDH
t
DACD
TB1 T2
t
AD
t
CSD
t
RWD
t
RSD
t t
RDS RDH
t
DACD
Rev. 4.0, 04/00, page 763 of 850