Hitachi SH7750 series Hardware Manual page 400

For wait control, waits specified by WCR2 and wait insertion by means of the 5'< pin can be
used.
In a read, one wait cycle is automatically inserted after address output, even if WCR2 is cleared to
0.
CKIO
/
D63–D0
RD/
DACKn
(DA)
(Single Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits)
Tm1 Tmd1w
A
Figure 13.52 MPX Interface Timing 1
Tmd1
D0
Rev. 4.0, 04/00, page 389 of 850