Hitachi SH7750 series Hardware Manual page 17

21.2.3 Bypass Register (SDBPR) ................................................................................... 708
21.3 Operation .......................................................................................................................... 709
21.3.1 TAP Control......................................................................................................... 709
21.3.2 H-UDI Reset ........................................................................................................ 710
21.3.3 H-UDI Interrupt ................................................................................................... 710
21.3.4 Bypass.................................................................................................................. 710
21.4 Usage Notes ...................................................................................................................... 711
Section 22 Pin Description
22.1 Pin Arrangement ............................................................................................................... 713
22.2 Pin Functions .................................................................................................................... 715
22.2.1 Pin Functions (256-Pin BGA).............................................................................. 715
22.2.2 Pin Functions (208-Pin QFP)............................................................................... 725
Section 23 Electrical Characteristics
23.1 Absolute Maximum Ratings ............................................................................................. 733
23.2 DC Characteristics ............................................................................................................ 734
23.3 AC Characteristics ............................................................................................................ 739
23.3.1 Clock and Control Signal Timing ........................................................................ 741
23.3.2 Control Signal Timing ......................................................................................... 755
23.3.3 Bus Timing .......................................................................................................... 757
23.3.4 Peripheral Module Signal Timing........................................................................ 806
23.3.5 AC Characteristic Test Conditions ...................................................................... 812
23.3.6 Delay Time Variation Due to Load Capacitance ................................................. 813
Appendix A Address List
Appendix B Package Dimensions
Appendix C Mode Pin Settings
&.,25(1% Pin Configuration
Appendix D
Appendix E Pin Functions
E.1 Pin States........................................................................................................................... 826
E.2 Handling of Unused Pins .................................................................................................. 829
Appendix F Synchronous DRAM Address Multiplexing Tables
Appendix G Product Code Lineup
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