H-Udi Reset; H-Udi Interrupt; Bypass - Hitachi SH7750 series Hardware Manual

21.3.2

H-UDI Reset

A power-on reset is effected by an SDIR command. A reset is effected by sending an H-UDI reset
assert command, and then sending an H-UDI reset negate command, from the H-UDI pin (see
figure 21.3). The interval required between the H-UDI reset assert command and the H-UDI reset
negate command is the same as the length of time the reset pin is held low in order to effect a
power-on reset.
H-UDI pin
Chip internal reset
CPU state
21.3.3

H-UDI Interrupt

The H-UDI interrupt function generates an interrupt by setting a command value in SDIR from the
H-UDI. The H-UDI interrupt is of general exception/interrupt operation type, with a branch to an
address based on VBR and return effected by means of an RTE instruction. The exception code
stored in control register INTEVT in this case is H'600. The priority of the H-UDI interrupt can be
controlled with bits 3 to 0 of control register IPRC.
The H-UDI interrupt request signal is asserted for about eight SH7750 Series on-chip peripheral
clock cycles after the command is set. The number of assertion cycles is determined by the ratio of
TCK to the on-chip peripheral clock frequency. As the assertion period is limited, the CPU may
sometimes miss a request. The H-UDI interrupt command automatically changes to the bypass
command immediately after being set.
21.3.4

Bypass

The H-UDI pins can be set to the bypass mode specified by JTAG by setting a command in SDIR
from the H-UDI.
Rev. 4.0, 04/00, page 710 of 850
H-UDI
reset assert
Normal
Figure 21.3 H-UDI Reset
H-UDI
reset negate
Reset Reset processing