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Table E.1
Pin States in Reset, Power-Down State, and Bus-Released State (cont)
Signal Name
:(:/&$6:/DQM7 O
:(9/&$69/DQM6 O
:(8/&$68/DQM5 O
:(7/&$67/DQM4 O
:(6/&$66/DQM3 O
:(5/&$65/DQM2 O
:(4/&$64/DQM1 O
:(3/&$63/DQM0 O
DACK1–DACK0
MD7/TXD
MD6/,2,649
MD5/5$65
MD4/&(5%
MD3/&(5$
CKIO
STATUS1–
STATUS0
,5/6–,5/3
NMI
'5(44–'5(43
DRAK1–DRAK0
MD0/SCK
RXD
SCK2/05(6(7
MD1/TXD2
MD2/RXD2
&765
MD8/5765
TCLK
Reset
(Power-On)
I/O
Master Slave
16
H
Z*
16
H
Z*
16
H
Z*
16
H
Z*
16
H
Z*
16
H
Z*
16
H
Z*
16
H
Z*
O
L
L
16
16
I/O
I*
I*
16
16
I
I*
I*
1
16
16
I/O*
I*
I*
2
16
16
I/O*
I*
I*
3
16
16
I/O*
I*
I*
O
O
O
O
O
O
16
16
I
I*
I*
16
16
I
I*
I*
16
16
I
I*
I*
O
L
L
16
16
I/O
I*
I*
16
16
I
I*
I*
16
16
I
I*
I*
16
16
I/O
I*
I*
16
16
I
I*
I*
16
16
I/O
I*
I*
16
16
I/O
I*
I*
16
16
I/O
I*
I*
Reset
(Manual)
Master Slave Sleep Standby
6
14
4
O*
Z*
O*
6
14
4
O*
Z*
O*
6
14
4
O*
Z*
O*
6
14
4
O*
Z*
O*
6
14
4
O*
Z*
O*
6
14
4
O*
Z*
O*
6
14
4
O*
Z*
O*
6
14
4
O*
Z*
O*
12
L
L
O*
12
12
12
Z*
Z*
Z*
13
13
13
I*
I*
I*
13
6
13
13
Z*
O*
Z*
Z*
13
13
13
Z*
H
Z*
Z*
13
13
13
Z*
H
Z*
Z*
11
11
ZO*
ZO*
ZO*
O
O
O
13
13
13
I*
I*
I*
13
13
13
I*
I*
I*
12
12
12
I*
I*
I*
4
L
L
O*
12
12
12
I*
I*
I*
O
12
12
12
I*
I*
I*
12
12
12
I*
I*
I*
12
12
12
Z*
Z*
Z*
12
12
12
I*
I*
I*
12
12
12
I*
I*
I*
O
12
12
12
I*
I*
I*
O
12
12
12
I*
I*
I*
O
Bus
Released Notes
14
5
14
Z*
O*
Z*
O*
14
5
14
Z*
O*
Z*
O*
14
5
14
Z*
O*
Z*
O*
14
5
14
Z*
O*
Z*
O*
14
5
14
Z*
O*
Z*
O*
14
5
14
Z*
O*
Z*
O*
14
5
14
Z*
O*
Z*
O*
14
5
14
Z*
O*
Z*
O*
12
8
12
Z*
O*
O*
12
8
12
O Z*
O*
Z*
O
13
13
I*
I*
4
13
5
13
O*
Z*
O*
Z*
O*
4
13
7
13
O*
Z*
H*
Z*
4
13
7
13
O*
Z*
H*
Z*
11
11
11
ZO*
ZO*
O
O
13
13
I*
I*
13
13
I*
I*
12
12
I*
I*
12
8
12
Z*
O*
O*
12
12
8
12
I*
Z*
O*
I*
O
12
12
I*
I*
12
12
I*
I*
12
8
12
O Z*
O*
Z*
O
12
12
I*
I*
12
12
8
12
I*
Z*
O*
I*
O
12
12
8
12
I*
Z*
O*
I*
O
12
12
I*
O
I*
O
Rev. 4.0, 04/00, page 827 of 850
5
5
5
5
5
5
5
5
DMAC
SCI
PCMCIA
(I/O)
5
DRAM2
PCMCIA
PCMCIA
INTC
INTC
DMAC
DMAC
SCI
SCI
SCIF
SCIF
SCIF
SCIF
SCIF
TMU
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