Hitachi SH7750 series Hardware Manual page 596

Superh risc engine

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Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used

to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty

(TDFE) flag in the serial status register (SCFSR2). The TDFE flag is set when the number of

transmit data bytes in SCFTDR2 is equal to or less than the trigger set number shown in the

following table.

Bit 5: TTRG1

Note: * Initial value. Figures in parentheses are the number of empty bytes in SCFTDR2 when the

flag is set.

Bit 3—Modem Control Enable (MCE): Enables the &765 and 5765 modem control signals.

Note: * &765 is fixed at active-0 regardless of the input value, and 5765 output is also fixed at 0.

Bit 2—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the

transmit FIFO data register and resets it to the empty state.

Bit 2: TFRST

Note: * A reset operation is performed in the event of a power-on reset or manual reset.

Bit 1—Receive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive

FIFO data register and resets it to the empty state.

Bit 1: RFRST

Note: * A reset operation is performed in the event of a power-on reset or manual reset.

Bit 4: TTRG0

Modem signals disabled*

Modem signals enabled

Reset operation disabled*

Reset operation enabled

Reset operation disabled*

Reset operation enabled

Transmit Trigger Number

(Initial value)

Rev. 4.0, 04/00, page 585 of 850

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