Examples Of Use - Hitachi SH7750 series Hardware Manual

Superh risc engine
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20.5

Examples of Use

Instruction Access Cycle Break Condition Settings
• Register settings: BASRA = H'80 / BARA = H'00000404 / BAMRA = H'00 /
BBRA = H'0014 / BASRB = H'70 / BARB = H'00008010 / BAMRB = H'01 /
BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0400
Conditions set: Independent channel A/channel B mode
 Channel A: ASID: H'80 / address: H'00000404 / address mask: H'00
Bus cycle: instruction access (post-instruction-execution), read (operand size not included
in conditions)
 Channel B: ASID: H'70 / address: H'00008010 / address mask: H'01
Data: H'00000000 / data mask: H'00000000
Bus cycle: instruction access (pre-instruction-execution), read (operand size not included in
conditions)
A user break is generated after execution of the instruction at address H'00000404 with
ASID = H'80, or before execution of an instruction at addresses H'00008000–H'000083FE
with ASID = H'70.
• Register settings: BASRA = H'80 / BARA = H'00037226 / BAMRA = H'00 /
BBRA = H'0016 / BASRB = H'70 / BARB = H'0003722E / BAMRB = H'00 /
BBRB = H'0016 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0008
Conditions set: Channel A → channel B sequential mode
 Channel A: ASID: H'80 / address: H'00037226 / address mask: H'00
Bus cycle: instruction access (pre-instruction-execution), read, word
 Channel B: ASID: H'70 / address: H'0003722E / address mask: H'00
Data: H'00000000 / data mask: H'00000000
Bus cycle: instruction access (pre-instruction-execution), read, word
The instruction at address H'00037266 with ASID = H'80 is executed, then a user break is
generated before execution of the instruction at address H'0003722E with ASID = H'70.
• Register settings: BASRA = H'80 / BARA = H'00027128 / BAMRA = H'00 /
BBRA = H'001A / BASRB = H'70 / BARB = H'00031415 / BAMRB = H'00 /
BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0000
Conditions set: Independent channel A/channel B mode
 Channel A: ASID: H'80 / address: H'00027128 / address mask: H'00
Bus cycle: CPU, instruction access (pre-instruction-execution), write, word
Rev. 4.0, 04/00, page 699 of 850

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