Hitachi SH7750 series Hardware Manual page 167

10. OCBI: 1 issue cycle
I
D
11. OCBP, OCBWB: 1 issue cycle
I
D
12. MOVCA.L: 1 issue cycle
I
D
13. TRAPA: 7 issue cycles
I
D
14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle
I
D
15. LDC to GBR: 3 issue cycles
I
D
16. LDC to SR: 4 issue cycles
I
D
17. LDC.L to DBR/Rp_BANK/SSR/SPC/VBR: 1 issue cycle
I
D
18. LDC.L to GBR: 3 issue cycles
I
D
Rev. 4.0, 04/00, page 152 of 850
EX
MA
S
MA
EX MA
S
MA
EX MA
S
MA
EX NA
S
D EX NA
D EX
EX NA
S
SX
SX
EX NA
S
D SX
SX
D
EX NA
S
D
SX
D
SX
D
EX MA
S
SX
SX
EX MA
S
SX
D
SX
D
Figure 8.2 Instruction Execution Patterns (cont)
MA
MA
MA
MA
S
NA
S
D EX NA
D EX
D
SX
MA
MA
MA
MA
S
NA
S
EX NA
S
D EX NA
S