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Series, the value actually written to the synchronous DRAM is the value of "X" shifted 2 bits to
the right.
For example, to write H'0230 to the area 2 SDMR register, arbitrary data is written to address
H'FF900000 (address "Y") + H'08C0 (value "X") (= H'FF9008C0). As a result, H'0230 is written
to the SDMR register. The range of value "X" is H'0000 to H'0FFC.
Similarly, to write H'0230 to the area 3 SDMR register, arbitrary data is written to address
H'FF940000 (address "Y") + H'08C0 (value "X") (= H'FF9408C0). As a result, H'0230 is written
to the SDMR register. The range of value "X" is H'0000 to H'0FFC.
The lower 16 bits of the address are set in the synchronous DRAM mode register.
For a 32-bit bus:
15
14
Address
For a 64-bit bus:
15
14
Address
LMODE: RAS-CAS latency
BL:
Burst length
WT:
Wrap type (0: Sequential)
BL
000: Reserved
001: Reserved
010: 4
011: 8
100: Reserved
101: Reserved
110: Reserved
111: Reserved
13
12
11
10
0
0
←→
13
12
11
10
0
0
0
←→
10 bits set in case of 64-bit bus width
LMODE
000: Reserved
001: 1
010: 2
011: 3
100: Reserved
101: Reserved
110: Reserved
111: Reserved
9
8
7
0
LMO
LMO
LMO
DE2
DE1
DE0
10 bits set in case of 32-bit bus width
9
8
7
LMO
LMO
LMO
WT
DE2
DE1
DE0
6
5
4
3
WT
BL2 BL1 BL0
6
5
4
3
BL2 BL1 BL0
Rev. 4.0, 04/00, page 303 of 850
2
1
0
2
1
0
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