Table of Contents
Advertisement
Bit 19—BREQ Enable (BREQEN): Indicates whether external requests can be accepted.
BREQEN is initialized to the external request acceptance disabled state by a power-on reset. It is
ignored in the case of a slave mode startup.
Bit 19: BREQEN
0
1
Bit 18—Partial-Sharing Bit (PSHR): Sets partial-sharing mode. PSHR is valid only in the case
of a master mode startup.
Bit 18: PSHR
0
1
Bit 17—Area 1 to 6 MPX Interface Specification (MEMMPX): Sets the MPX interface when
areas 1 to 6 are set as SRAM interface (or burst ROM interface). MEMMPX is initialized by a
power-on reset.
Bit 17: MEMMPX
0
1
Bit 15—High Impedance Control (HIZMEM): Specifies the state of address and other signals
(A[25:0], %6, &6Q, RD/:5, &(5$, &(5%) in standby mode.
Bit 15: HIZMEM
0
1
Description
External requests are not accepted
External requests are accepted
Description
Master mode
Partial-sharing mode
Description
SRAM interface (or burst ROM interface) is selected when areas 1 to 6 are
set as SRAM interface (or burst ROM interface)
MPX interface is selected when areas 1 to 6 are set as SRAM interface (or
burst ROM interface)
Description
The A[25:0], %6, &6Q, RD/:5, &(5$, and &(5% signals go to high-
impedance (High-Z) in standby mode and when the bus is released
The A[25:0], %6, &6Q, RD/:5, &(5$, and &(5% signals drive in standby
mode
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Rev. 4.0, 04/00, page 275 of 850
Advertisement
Table of Contents
