Hitachi SH7750 series Hardware Manual page 353

Tpc Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2
CKIO
r c1 c2 c3 c4
A25–A0
RD/
D63–D0
d1 d2 d3 d4
(read)
D63–D0
d1 d2 d3 d4
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Figure 13.20 (1) DRAM Burst Bus Cycle, RAS Down Mode Start
(Fast Page Mode, RCD = 0, Anw = 0)
Rev. 4.0, 04/00, page 342 of 850