Table of Contents
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Table 1.1
SH7750 Series Features (cont)
Item
Bus state
controller (BSC)
Direct memory
access controller
(DMAC)
Timer unit (TMU)
Realtime clock
(RTC)
Rev. 4.0, 04/00, page 6 of 850
Features
•
Supports external memory access
64/32/16/8-bit external data bus
•
External memory space divided into seven areas, each of up to 64
Mbytes, with the following parameters settable for each area:
Bus size (8, 16, 32, or 64 bits)
Number of wait cycles (hardware wait function also supported)
Connection of DRAM, synchronous DRAM, and burst ROM possible
by setting space type
Supports fast page mode and DRAM EDO
Supports PCMCIA interface
Chip select signals (&63 to &69) output for relevant areas
•
DRAM/synchronous DRAM refresh functions
Programmable refresh interval
Supports CAS-before-RAS refresh mode and self-refresh mode
•
DRAM/synchronous DRAM burst access function
•
Big endian or little endian mode can be set
•
4-channel physical address DMA controller
•
Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes
•
Address modes:
1-bus-cycle single address mode
2-bus-cycle dual address mode
•
Transfer requests: External, on-chip module, or auto-requests
•
Bus modes: Cycle-steal or burst mode
•
Supports on-demand data transfer
•
3-channel auto-reload 32-bit timer
•
Input capture function
•
Choice of seven counter input clocks
•
On-chip clock and calendar functions
•
Built-in 32 kHz crystal oscillator with maximum 1/256 second resolution
(cycle interrupts)
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