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Bit 15: NMIL
0
1
Bit 14—NMI Interrupt Mask (MAI): Specifies whether or not all interrupts are to be masked
while the NMI pin input level is low, irrespective of the CPU's SR.BL bit.
Bit 14: MAI
0
1
Note: * NMI interrupts are accepted in normal operation and in sleep mode.
In standby mode, all interrupts are masked, and standby is not cleared, while the NMI pin is
low.
Bit 9—NMI Block Mode (NMIB): Specifies whether an NMI request is to be held pending or
detected immediately while the SR.BL bit is set to 1.
Bit 9: NMIB
0
1
Notes: 1. If interrupt requests are enabled while SR.BL = 1, the previous exception information
will be lost, and so must be saved beforehand.
2. This bit is cleared automatically by NMI acceptance.
Bit 8—NMI Edge Select (NMIE): Specifies whether the falling or rising edge of the interrupt
request signal to the NMI pin is detected.
Bit 8: NMIE
0
1
Bit 7—IRL Pin Mode (IRLM): Specifies whether pins ,5/6–,5/3 are to be used as level-
encoded interrupt requests or as four independent interrupt requests.
Bit 7: IRLM
0
1
Description
NMI pin input level is low
NMI pin input level is high
Description
Interrupts enabled even while NMI pin is low
Interrupts disabled while NMI pin is low*
Description
NMI interrupt requests held pending while SR.BL bit is set to 1
NMI interrupt requests detected while SR.BL bit is set to 1
Description
Interrupt request detected on falling edge of NMI input
Interrupt request detected on rising edge of NMI input
Description
,5/ pins used as level-encoded interrupt requests
,5/ pins used as four independent interrupt requests
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Rev. 4.0, 04/00, page 671 of 850
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