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The following three kinds of operation can be used on the OC address array:
1. OC address array read
The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the
entry set in the address field. In a read, associative operation is not performed regardless of
whether the association bit specified in the address field is 1 or 0.
2. OC address array write (non-associative)
The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to
the entry set in the address field. The A bit in the address field should be cleared to 0.
When a write is performed to a cache line for which the U bit and V bit are both 1, after write-
back of that cache line, the tag, U bit, and V bit specified in the data field are written.
3. OC address array write (associative)
When a write is performed with the A bit in the address field set to 1, the tag stored in the
entry specified in the address field is compared with the tag specified in the data field. If the
MMU is enabled at this time, comparison is performed after the virtual address specified by
data field bits [31:10] has been translated to a physical address using the UTLB. If the
addresses match and the V bit is 1, the U bit and V bit specified in the data field are written
into the OC entry. This operation is used to invalidate a specific OC entry. In other cases, no
operation is performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit,
write-back is performed. If an UTLB miss occurs during address translation, or the comparison
shows a mismatch, an exception is not generated, no operation is performed, and the write is
not executed. If a data TLB multiple hit exception occurs during address translation,
processing switches to the data TLB multiple hit exception handling routine.
31
Address field
1 1 1 1 0 1 0 0
31
Data field
V
: Validity bit
U
: Dirty bit
A
: Association bit
: Reserved bits (0 write value, undefined read value)
24
23
Tag
Figure 4.8 Memory-Mapped OC Address Array
14
13
Entry
10 9
Rev. 4.0, 04/00, page 77 of 850
5 4 3 2 1 0
A
2
1 0
U
V
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