Hitachi SH7750 series Hardware Manual page 500

CLK
DBREQ
BAVL
TR
A25–A0
D63–D0
RAS, CAS,
WE
Figure 14.38 Write to Synchronous DRAM Non-Precharge Bank (Row Miss)
CLK
DBREQ
BAVL
TR
A25–A0
D63–D0
RAS, CAS,
WE
Figure 14.39 Write to Synchronous DRAM (Row Hit)
Transfer requests can be accepted
RA
BA
PCH
CA
D0 D1 D2 D3
WT
CA
D0 D1 D2 D3
WT
Rev. 4.0, 04/00, page 489 of 850