Hitachi SH7750 series Hardware Manual page 356

Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce
CKIO
c1 c2 c3 c4
A25–A0
RD/
End of RAS down mode
D63–D0
d1 d2 d3 d4
(read)
DACKn
(SA: IO ← memory)
Figure 13.20 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(EDO Mode, RCD = 0, Anw = 0)
Rev. 4.0, 04/00, page 345 of 850