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SH7750 Series
Figure 13.9 Example of 8-Bit Data Width SRAM Connection
Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2
settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a
software wait is inserted in accordance with that specification. For details, see section 13.2.4, Wait
Control Register 2 (WCR2).
The specified number of Tw cycles are inserted as wait cycles using the basic interface wait
timing shown in figure 13.10.
A16
A0
D7
D0
128K × 8-bit
SRAM
A16
A0
I/O7
I/O0
Rev. 4.0, 04/00, page 329 of 850
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