Tm1
Tmd1w
Tmd1
Tmd2w
Tmd2
Tmd3
Tmd4w
Tmd4
CKIO
/
D63–D0
A
D0
D1
D2
D3
RD/
DACKn
(DA)
Figure 13.57 MPX Interface Timing 6
(Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 64 Bits,
Transfer Data Size: 32 Bytes)
Rev. 4.0, 04/00, page 394 of 850