Hitachi SH7750 series Hardware Manual page 301

Bits 2 to 0—Area 0 Burst Pitch (A0B2–A0B0): These bits specify the burst pitch to in burst
ROM interface setting.
Bit 2: A0B2 Bit 1: A0B1
0 0
1
1 0
1
• When MPX Interface is Set (Areas 0 to 6)
Bit 4n + 2: Bit 4n + 1:
AnW2 AnW1
0 0
1
1 0
1
(n = 6 to 0)
Rev. 4.0, 04/00, page 290 of 850
Bit 0: A0B0
0
1
0
1
0
1
0
1
Bit 4n:
AnW0 Read
0 1
1
0 2
1 3
0 1
1
0 2
1 3
Description
Burst Cycle (Excluding First Cycle)
Wait States Inserted from
Second Data Access Onward
0
1
2
3
4
5
6
7 (Initial value)
Description
Inserted Wait States
1st Data
2nd Data
Write Onward
0 0
1
2
3
0 1
1
2
3
5'< Pin 5'<
5'< 5'<
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
5'< Pin 5'<
5'< 5'<
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled