Memory-Mapped Registers - Hitachi SH7750 series Hardware Manual

When an FPU operation instruction is executed, the FPU exception cause field is cleared to
zero first. When the next FPU exception is occured, the corresponding bits in the FPU
exception cause field and FPU exception flag field are set to 1. The FPU exception flag field
holds the status of the exception generated after the field was last cleared.
• RM: Rounding mode
RM = 00: Round to Nearest
RM = 01: Round to Zero
RM = 10: Reserved
RM = 11: Reserved
• Bits 22 to 31: Reserved
Floating-point communication register, FPUL (32 bits, initial value undefined): Data transfer
between FPU registers and CPU registers is carried out via the FPUL register.
Programming Note: When SZ = 1 and big endian mode is selected, FMOV can be used for
double-precision floating-point load or store operations. In little endian mode, two 32-bit data size
moves must be executed, with SZ = 0, to load or store a double-precision floating-point number.
2.3

Memory-Mapped Registers

Appendix A shows the control registers mapped to memory. The control registers are double-
mapped to the following two memory areas. All registers have two addresses.
H'1F00 0000–H'1FFF FFFF
H'FF00 0000–H'FFFF FFFF
These two areas are used as follows.
• H'1F00 0000–H'1FFF FFFF
This area must be accessed in address translation mode using the TLB. Since external memory
is defined as a 29-bit address space in the SH7750 architecture, the TLB's physical page
numbers do not cover a 32-bit address space. In address translation, the page numbers of this
area can be set in the corresponding field of the TLB by accessing a memory-mapped register.
The page numbers of this area should be used as the actual page numbers set in the TLB.
When address translation is not performed, the operation of accesses to this area is undefined.
• H'FF00 0000–H'FFFF FFFF
Access to area H'FF00 0000–H'FFFF FFFF in user mode will cause an address error. Memory-
mapped registers can be referenced in user mode by means of access that involves address
translation.
Rev. 4.0, 04/00, page 20 of 850