Hitachi SH7750 series Hardware Manual page 770

CKIO
A25
RD/
D63
(read)
D63
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Figure 23.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time
Rev. 4.0, 04/00, page 762 of 850
TS1
t
AD
–
A0
t
CSD
t
RWD
t
RSD
–
D0
t
WED1
t
WDD
–
D0
t
BSD
t
DACD
t
DACD
Insertion, AnS = 1, AnH = 1)
T1 T2 TH1
t
RSD
t
RDS
t t
WEDF WEDF
t
WDD
t
BSD
t
DACD
t
t
DACDF
t
AD
t
CSD
t
RWD
t
RSD
t
RDH
t
WDD
DACD
t
DACDF
t
DACD