Table of Contents
Advertisement
BE
EDOMODE
0
0
1
1
0
1
Note: * In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit
bus.
Bits 8 and 7—Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and
synchronous DRAM. This setting has priority over the BCR2 register setting.
Bit 8: SZ1
Bit 7: SZ0
0
0
1
1
0
1
Bits 6 to 3—Address Multiplexing (AMXEXT, AMX2–AMX0): These bits specify address
multiplexing for DRAM and synchronous DRAM. The address shift value is different for the
DRAM interface and the synchronous DRAM interface.
• For DRAM Interface:
Bit 6:
Bit 5:
AMXEXT
AMX2
0*
0
1
Note: * When the DRAM interface is used, clear the AMXEXT bit to 0.
8/16/32/64-Bit Transfer
Single
Setting prohibited
Single/fast page*
EDO
DRAM
64 bits
Reserved (Setting prohibited)
16 bits
32 bits
Bit 4:
Bit 3:
AMX1
AMX0
0
0
1
1
0
1
0
0
1
1
0
1
32-Byte Transfer
Single
Setting prohibited
Fast page
EDO
Description
SDRAM
64 bits
Reserved (Setting prohibited)
Reserved (Setting prohibited)
32 bits
Description
DRAM
8-bit column address product
9-bit column address product
10-bit column address product
11-bit column address product
12-bit column address product
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Rev. 4.0, 04/00, page 297 of 850
(Initial value)
Advertisement
Table of Contents
