Hitachi SH7750 series Hardware Manual page 106

Pipeline flow:
Instruction n
Instruction n+1
Instruction n+2
Instruction n+3
Order of detection:
General illegal instruction exception (instruction n+1) and
TLB miss (instruction n+2) are detected simultaneously
TLB miss (instruction n)
Order of exception handling:
TLB miss (instruction n)
Re-execution of instruction n
General illegal instruction exception
(instruction n+1)
Re-execution of instruction n+1
TLB miss (instruction n+2)
Re-execution of instruction n+2
Execution of instruction n+3
Figure 5.3 Example of General Exception Acceptance Order
Rev. 4.0, 04/00, page 90 of 850
TLB miss (data access)
IF ID EX MA
IF ID EX MA
General illegal instruction exception
TLB miss (instruction access)
IF ID EX
IF ID
WB
WB
MA WB
EX MA WB
Program order
1
2
3
4
IF: Instruction fetch
ID: Instruction decode
EX: Instruction execution
MA: Memory access
WB: Write-back