Break Address Register B (Barb); Break Asid Register B (Basrb); Break Address Mask Register B (Bamrb); Break Data Register B (Bdrb) - Hitachi SH7750 series Hardware Manual

20.2.6

Break Address Register B (BARB)

BARB is the channel B break address register. The bit configuration is the same as for BARA.
20.2.7

Break ASID Register B (BASRB)

BASRB is the channel B break ASID register. The bit configuration is the same as for BASRA.
20.2.8

Break Address Mask Register B (BAMRB)

BAMRB is the channel B break address mask register. The bit configuration is the same as for
BAMRA.
20.2.9

Break Data Register B (BDRB)

Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Note: *: Undefined
Break data register B (BDRB) is a 32-bit readable/writable register that specifies the data (bits 31–
0) to be used in the channel B break conditions. BDRB is not initialized by a power-on reset or
manual reset.
31 30
BDB31 BDB30
* *
R/W R/W
23 22
BDB23 BDB22
* *
R/W R/W
15 14
BDB15 BDB14
* *
R/W R/W
7 6
BDB7 BDB6
* *
R/W R/W
29 28
BDB29 BDB28
* *
R/W R/W
21 20
BDB21 BDB20
* *
R/W R/W
13 12
BDB13 BDB12
* *
R/W R/W
5 4
BDB5 BDB4
* *
R/W R/W
27 26
BDB27 BDB26
* *
R/W R/W
19 18
BDB19 BDB18
* *
R/W R/W
11 10
BDB11 BDB10
* *
R/W R/W
3 2
BDB3 BDB2
* *
R/W R/W
Rev. 4.0, 04/00, page 685 of 850
25 24
BDB25 BDB24
* *
R/W R/W
17 16
BDB17 BDB16
* *
R/W R/W
9 8
BDB9 BDB8
* *
R/W R/W
1 0
BDB1 BDB0
* *
R/W R/W