Hitachi SH7750 series Hardware Manual page 103

Table 5.2 Exceptions (cont)
Exception Execution
Category Mode
Interrupt Completion
type
Exception
Nonmaskable interrupt
External IRL3–IRL0
interrupts
Peripheral TMU0
module
TMU1
interrupt
TMU2
(module/
source)
RTC
SCI
WDT
REF
H-UDI
GPIO
Priority Priority
Level Order
3 —
0 4 *2
1
2
3
4
5
6
7
8
9
A
B
C
D
E
TUNI0 4 *2
TUNI1
TUNI2
TICPI2
ATI
PRI
CUI
ERI
RXI
TXI
TEI
ITI
RCMI
ROVI
H-UDI
GPIOI
Vector
Address Offset
(VBR) H'600
(VBR) H'600
(VBR) H'600
Rev. 4.0, 04/00, page 87 of 850
Exception
Code
H'1C0
H'200
H'220
H'240
H'260
H'280
H'2A0
H'2C0
H'2E0
H'300
H'320
H'340
H'360
H'380
H'3A0
H'3C0
H'400
H'420
H'440
H'460
H'480
H'4A0
H'4C0
H'4E0
H'500
H'520
H'540
H'560
H'580
H'5A0
H'600
H'620