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master other than the SH7750 Series requesting the bus, or the bus arbiter, and returning the
bus to the SH7750 Series.
TRr1
CKIO
A25–A0
RD/
D63–D0
Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time
(at least 100 µs or 200 µs) during which no access can be performed be provided, followed by at
least the prescribed number (usually 8) of dummy CAS-before-RAS refresh cycles. As the bus
state controller does not perform any special operations for a power-on reset, the necessary power-
on sequence must be carried out by the initialization program executed after a power-on reset.
TRr2
TRr3
TRr4
Figure 13.23 DRAM Self-Refresh Cycle Timing
TRr5
Trc
Trc
Rev. 4.0, 04/00, page 349 of 850
Trc
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