Hitachi SH7750 series Hardware Manual page 409

Tm1 Tmd1w Tmd1w Tmd1 Tmd2
CKIO
/
D31–D0
A D0 D1
RD/
DACKn
(DA)
Figure 13.61 MPX Interface Timing 2
(Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits,
Transfer Data Size: 64 Bytes)
Rev. 4.0, 04/00, page 398 of 850