Hitachi SH7750 series Hardware Manual page 769

CKIO
A25–A0
RD/
D63–D0
(read)
D63–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Note: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
Figure 23.17 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)
T1 Tw
t
AD
t
CSD
t
RWD
t t
RSD RSD
t
WED1
t
WEDF
t t
WDD WDD
t t
BSD BSD
t
RDYS
t
RDYS
t
DACD
t
DACD
t
DACDF
t
DACD
Twe T2
t
AD
t
CSD
t
RWD
t
RSD
t
RDS
t
WEDF
t
WDD
t
RDYH
t
RDYH
t
DACD
t
DACDF
t
DACD
Rev. 4.0, 04/00, page 761 of 850
t
RDH