Hitachi SH7750 series Hardware Manual page 297

Superh risc engine

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Bits 22 to 20—Area 5 Burst Pitch (A5B2–A5B0): These bits specify the number of wait states to

be inserted from the second data access onward in a burst transfer.

Bit 22: A5B2

Bit 21: A5B1

Bits 19 to 17—Area 4 Wait Control (A4W2–A4W0): These bits specify the number of wait

states to be inserted for area 4.

Bit 19: A4W2

Bit 18: A4W1

Bits 16 and 12—Reserved: These bits are always read as 0, and should only be written with 0.

Rev. 4.0, 04/00, page 286 of 850

Wait States Inserted from

Bit 20: A5B0

Second Data Access Onward

7 (Initial value)

Bit 17: A4W0

Inserted Wait States

15 (Initial value)

Burst Cycle (Excluding First Cycle)

Sh7750sSh7750