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16.2.4
Transmit FIFO Data Register (SCFTDR2)
Bit:
R/W:
SCFTDR2 is a 16-stage FIFO register that stores data for serial transmission.
If SCTSR2 is empty when transmit data has been written to SCFTDR2, the SCIF transfers the
transmit data written in SCFTDR2 to SCTSR2 and starts serial transmission.
SCFTDR2 is a write-only register, and cannot be read by the CPU.
The next data cannot be written when SCFTDR2 is filled with 16 bytes of transmit data. Data
written in this case is ignored.
The contents of SCFTDR2 are undefined after a power-on reset or manual reset.
16.2.5
Serial Mode Register (SCSMR2)
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
SCSMR2 is a 16-bit register used to set the SCIF's serial transfer format and select the baud rate
generator clock source.
SCSMR2 can be read or written to by the CPU at all times.
SCSMR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0.
7
6
W
W
15
14
—
—
0
0
R
R
7
6
—
CHR
PE
0
0
R
R/W
R/W
5
4
W
W
13
12
—
—
0
0
R
R
5
4
O/(
STOP
0
0
R/W
R/W
3
2
W
W
11
10
—
—
0
0
R
R
3
2
—
CKS1
0
0
R
R/W
Rev. 4.0, 04/00, page 571 of 850
1
0
W
W
9
8
—
—
0
0
R
R
1
0
CKS0
0
0
R/W
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