Hitachi SH7750 series Hardware Manual page 761

Stable input clock
EXTAL input
PLL synchronization
PLL output,
CKIO output
Internal clock
STATUS1–
Normal
STATUS0
Note: When external clock from EXTAL is input
Figure 23.9 PLL Synchronization Settling Time in Case of 5(6(7
Stable input clock
EXTAL input
PLL synchronization
PLL output,
CKIO output
Internal clock
STATUS1–
Normal
STATUS0
Note: When external clock from EXTAL is input
Figure 23.10 PLL Synchronization Settling Time in Case of IRL Interrupt
Reset or NMI
interrupt request
Standby
–
interrupt request
t
IRLSTB
Standby
Stable input clock
× 2
t
PLL synchronization
PLL
5(6(7 or NMI Interrupt
5(6(7 5(6(7
Stable input clock
× 2
PLL synchronization
t
PLL
Rev. 4.0, 04/00, page 753 of 850
Normal
Normal