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Bits 11 to 9—Area 2 Wait Control (A2W2–A2W0): These bits specify the number of wait states
to be inserted for area 2. External wait input is only enabled when normal memory is used, and is
ignored when DRAM or synchronous DRAM is used.
• When SRAM Interface is Set
Bit 11: A2W2
Bit 10: A2W1
0
0
1
1
0
1
• When DRAM or Synchronous DRAM Interface is Set*
Bit 11: A2W2
Bit 10: A2W1
0
0
1
1
0
1
Note: * External wait input is always ignored.
Rev. 4.0, 04/00, page 288 of 850
Bit 9: A2W0
Inserted Wait States
0
0
1
1
0
2
1
3
0
6
1
9
0
12
1
15 (Initial value)
DRAM &$6
Bit 9: A2W0
Assertion Width
0
1
1
2
0
3
1
4
0
7
1
10
0
13
1
16
Description
Description
&$6
&$6
&$6
Synchronous DRAM
&$6 Latency Cycles
&$6
&$6
&$6
Inhibited
1
2
3
4
5
Inhibited
Inhibited
5'< Pin
5'<
5'<
5'<
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
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